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A Defect-Tolerant Computer Architecture: Opportunities For Nanotechnology

J. Heath, P. Kuekes, G. S. Snider, R. Williams
Published 1998 · Computer Science

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Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system.
This paper references
Rent's rule was discovered by Richard Rent at IBM in the 1960s. Although it was never published by Rent, subsequent work has confirmed its validity
(1971)
J. Appl. Phys
P D Tougaw (1994)
An especially good introduction to information science for physical scientists is R. P. Feynman, Lectures in Computation
(1996)
Appl. Phys. Lett
R H Chen (1996)
10.1063/1.115637
Single‐electron transistor logic
R. Chen (1996)
11th Eurographics Workshop on Computer Graphics Hardware
U Kanus (1996)
Res. Dev
R Landauer (1961)
This small percentage of area devoted to logic holds true for all VLSI chips built today
International Conference on Wafer Scale Integration
堀口 進 (1994)
10.1063/1.355880
AMORPHOUS PHASE FORMATION BY ION BOMBARDMENT : DIRECT COMPARISON BETWEEN ION IMPLANTATION AND ION-BEAM MIXING
L. Thomé (1994)
IEEE Spectrum
R R Schaller (1997)
Proc. First Annual Symposium On Computer Architecture
L R Goke (1973)
HP scientists chose a fat-tree architecture with larger than necessary Rent's rule exponents to enable fast compilation
This version of Teramac was running a DNA string matching algorithm. For further detail on this algorithm
R J Lipton (1985)
Proc. IEEE 78
C Mead (1990)
R . R . Schaller , IEEE Spectrum 34 , 53 ( June 1997 ) . 3 . R . Landauer
A. J. G. Hey (1961)
Proc. IEEE Symp. FPGA's for Custom Computing Machines
W B Culbertson (1997)
10.1109/TC.1984.1676460
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
B. Krishnamurthy (1984)
10.1126/SCIENCE.3755256
Computing with neural circuits: a model.
J. Hopfield (1986)
We thank W. Robinett for helpful comments on the manuscript acknowledges support from an NSF-GOALI grant and the Hewlett Packard Corporation during the writing of this manuscript
Chem. Phys. Lett
A Aviram (1974)
IEEE Trans. Comput. C34
C E Leiserson (1985)
IEEE Trans. Comput. C
B Krishnamurthy (1984)
AND NOTES
IEEE Transactions on VLSI Systems
N J Howard (1994)



This paper is referenced by
10.1016/J.MATERRESBULL.2004.10.013
Preparation of VO2 nanowires and their electric characterization
Xingcai Wu (2005)
10.1007/1-4020-8068-9_3
Defect tolerance at the end of the roadmap
Mahim Mishra (2003)
10.1088/0957-4484/15/4/019
A short review of nanoelectronic architectures
M. Forshaw (2004)
10.1002/cta.282
Neuromorphic architectures for nanoelectronic circuits
Özgür Türel (2004)
10.1109/TNANO.2004.834192
Markov chains and probabilistic computation-a general framework for multiplexed nanoelectronic systems
Yan Qi (2005)
10.1002/ADMA.200401593
One-dimensional assemblies of nanoparticles: Preparation, properties, and promise
Z. Tang (2005)
10.1145/1168857.1168868
Ultra low-cost defect protection for microprocessor pipelines
S. Shyam (2006)
Nanowire alignment and patterning via evaporation-induced directed assembly
Farag Abdelsalam (2011)
10.1038/35018259
Chemistry meets computing
P. Ball (2000)
Array-Based Architecture for FET-Based,
Nanoscale Electronics (2003)
10.1109/tmtt.2006.872070
A novel wireless interconnect technology using impulse radio for interchip communications
Yuanjin Zheng (2006)
Constructing Dynamic Multiple-Input Multiple-Output Logic
Gates (2014)
Contents 1 Preface 2 2 Performance comparison of CMOS , RTD , SET and QCA devices against a standard
()
Nanoelectronic Adaptive Systems
J. Fortes (2003)
10.1007/s10836-006-0552-x
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
J. Brown (2007)
Nonlinear Dynamics of Memristor Based 2 nd and 3 rd Order Oscillators
King Abdullah (2011)
Iterative heuristics for CMOL hybrid CMOS/nanodevices cells mapping
Abdalrahman M. Arafeh (2012)
Electrical, Thermal, Structural and Optical Properties of Li(x) FeO2 (1-x) Nanorods and its Applications
V. Selvamurugan (2014)
10.1126/SCIENCE.285.5426.391
Electronically configurable molecular-based logic gates
Collier (1999)
10.1109/SiPS.2013.6674529
Constructing spare sharing networks for reliability enhancement of scalable systems
Soroush Khaleghi (2013)
10.1002/9781118958254.CH19
19. Atomic Switch
Tsuyoshi Hasegawa and (2014)
Recent Developments, Issues and Challenges for Lithography in ULSI Fabrication
R. Panwar (2012)
10.23956/IJERMT.V6I8.145
A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage
S. Ravichand (2018)
10.1016/J.JCRYSGRO.2004.09.080
Well-aligned zinc oxide nanorods and nanowires prepared without catalyst
F. Liu (2005)
10.1016/J.SYNTHMET.2009.02.046
The effect of the carbon nanotubes surface oxidation on the morphology and properties of poly(N-vinylcarbazole) coated multi-walled carbon nanotube nanocables
A. Maity (2009)
10.1097/00006123-200110000-00002
2001: Things to Come
M. Apuzzo (2001)
Defect-tolerant computing based on an asynchronous cellular automaton
T. Isokawa (2003)
10.1109/ISVLSI.2003.1183346
Future challenges in VLSI system design
J. Fortes (2003)
10.1007/BF03180021
Evolution of SoC technology and architectures for telecom applications
H. Fanet (2004)
10.1088/1742-5468/2004/11/P11003
Optimal static and dynamic recycling of defective binary devices
D. Challet (2004)
10.1145/1120725.1120857
Fault tolerant nanoelectronic processor architectures
W. Rao (2005)
10.1016/J.ACA.2006.01.051
Unimolecular rectifiers: methods and challenges.
R. Metzger (2006)
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